This invention relates to an inductor used for a high frequency circuit such as a mobile communication apparatus and instruments. More particularly, it relates to a laminated or multi-layered inductor having a miniaturized configuration and for a high frequency application and a method of producing such an inductor.
A laminated inductor, which is illustrated at reference numeral 2 in FIGS. 14(a) and 14(b), is known to have a structure of a chip component (of semiconductor integrated circuits) which permits xe2x80x9csurface mountingxe2x80x9d so that it can be mounted on printed circuit boards, etc. The laminated inductor 1 has terminal electrodes 4, 5 at opposed ends of the chip for connection with outer circuits, and a coil 3 in the chip so that ends of the coil 3 extend outside to be connected with the outer circuits. The coil 3 is formed such that electrically insulating layers of either magnetic material or non-magnetic material and conductive patterns are alternately superimposed or laminated with each other, and the ends of each of the conductive patterns are connected in turn to form a laminated construction.
Soldering properties of the terminal electrodes 4, 5 at the time of surface mounting are largely dominant or influential to a reliability of the chip components and, therefore, in order to ascertain a suitable bonding strength, the terminal electrodes 4, 5 are formed into a box-like structure to enclose the end surfaces of the chip component so that the box-like structure covers the side surfaces and upper and lower surfaces of the chip, as illustrated in FIGS. 14(a) and 14(b).
However, in the box-like structure of the electrodes described above, its end portions are extended inwardly toward the coil 3 in the chip so that the terminal electrodes 4, 5 are positioned closer to each other. Therefore, it is likely that a stray capacitance C is generated between the terminal electrodes 4, 5 and the coil portions (that is, the upper-right and lower-left portions of the box-like structure of FIG. 14(b)) where an electric potential is relatively large. Consequently, the resonance frequency is not as increased as expected by the influence of the stray capacitance C, and the Q-factor of the coil is lowered. Thus, there is a problem that it is difficult to provide a suitable application for a high frequency. Particularly, through a recent diffusion and spread of personal computers (PC) and local area network (LAN), a large demand has been made to use an ultra-high frequency band exceeding 2 GHz, and it has been necessary to meet with the requirement of further and higher frequency applications due to an increase of resonance frequency, in the chip type laminated inductor.
In order to lower a stray capacitance, it is sufficient to minimize the extended portions of the terminal electrodes 4, 5. In the conventional method of forming the terminal electrodes 4, 5, a complex technique, which is called a dip method, has been used to dip a tip end into a predetermined depth of a paste for the terminals, but this method has some difficulties in seeking a high dimensional accuracy due to stain and soil of the paste. Accordingly, it has been extremely difficult to provide small sized electrodes. Furthermore, reduction of the extended portions of the terminal electrodes results in another disadvantage of lowering the bonding strength at the time of the mounting or packaging of parts and elements.
At the time of dipping in the dip method, it is necessary to have a portion in the chip for holding the chip itself. However, in the case of a micro-structured chip such as, for example, Type 0603 (that is, 0.6 mmxc3x970.3 mmxc3x970.3 mm), there is less space in the chip itself for the holding portion and, therefore, the electrode structure as described above has been a bottle neck for meeting the requirement of micro-structure or micro-miniaturization. Thus, the conventional laminated inductor has serious problems with respect to reliability, performance capability and production efficiency in coping with the recent requirement of miniaturization, thinner designing, higher speed operation, etc.
It is, therefore, a primary object of the present invention to provide, in view of the problems and difficulties in the conventional structure, an improvement in a laminated inductor.
Another object of the present invention is to provide a new laminated inductor, which permits reduction of stray capacitance between the coil and the terminal electrodes so that the inductor is adaptable for a high frequency application.
A further object of the present invention is to provide an improved laminated inductor which has a suitable bonding strength at the chip mounting step and which meets the requirements of micro-miniaturization.
Another object of the invention is to provide a method of forming the improved laminated inductor described above.
According to a first aspect of the present invention, there is provided a laminated inductor comprising a plurality of electrically insulating layers (2), a plurality of electrically conductive patterns, and terminal electrodes. The electrically insulating layers and the conductive patterns are alternately superimposed with each other, and the electrically conductive patterns are connected with each other at the ends thereof to form a coil (3) in a laminated form. The terminal electrodes (4, 5) are arranged at opposed end portions of a chip, and a starting end and a terminal end of the coil extend, to connect the terminal electrodes. The terminal electrodes are formed on at least opposed end surfaces (1d) and a lower surface (1b) of the chip.
According to a modification of the structure of the invention described above, the terminal electrodes are formed not only on the opposed end surface and the lower surface of the chip but also on an upper surface of the chip.
FIG. 3 shows a case in which no terminal electrode is provided on the upper surface and the side surface of the chip, and FIG. 4 shows a case in which no terminal electrode is provided on the side surface of the chip. In the electrode structure of either case, distance between the coil and the extended portion of the terminal electrode can be reduced relative to the conventional structure. Therefore, a stray capacitance between the coil and the electrode can be reduced so that the structure of the present invention can meet with the requirement of high frequency applications.
In a second aspect of the invention, the terminal electrodes (4, 5) on both the upper and lower surfaces (1a, 1b) of the chip is formed during a laminating process of production.
By forming the electrodes on the upper and lower surfaces of the chip in the process of the lamination for forming the coil, it is sufficient to apply an electrode paste to the limited surface to which the conductive material is coupled. In other words, the application of the electrode paste can be limited to the connecting portion of the conductive member. Therefore, it is not necessary to prepare expensive equipment for controlling a flow or running the paste extensively to an unnecessary portion which has been needed in the conventional dip method. Thus, the production procedure can be simplified to provide reduction in manufacturing cost.
In a third aspect of the invention, the terminal electrode surface on the upper surface of the chip is made smaller in size than the terminal electrode surface on the lower surface of the chip.
With respect to the size of the terminal electrodes described above, since electrical measurements are generally conducted by contacting a measurement terminal to an upper surface of the chip, a relatively large terminal electrode of the upper surface will be convenient to proceed the contact of the measurement terminal onto the electrode. However, providing a large terminal electrode causes generation of a stray capacitance. In the embodiment of the invention, as shown in FIG. 5, the electrode on the upper surface of the chip is designed to be smaller than the electrode on the lower surface of the chip. Consequently, there is less influence of a stray capacitance, with the contact of the measurement terminal to the electrode of the upper surface being maintained. This will increase or raise a resonance frequency and improve a Q-factor of the coil.
According to a fourth aspect of the invention, a terminal electrode on the upper surface where an upper end of the coil is directed out is formed larger than the terminal electrode of the other terminal electrode on the same upper surface so that directional target can be obtained for taking out the wound coil.
In the structure described above, as the difference in the electric potential of the conductive members is larger, the stray capacitance between the conductive members becomes more remarkable. Therefore, if a terminal electrode is formed on the upper surface of the chip, then even though a terminal electrode having a smaller potential difference on the side of the pulled-out pattern is larger than the other terminal electrode of larger potential difference, there is less or substantially no increase in stray capacitance. FIG. 6 shows the difference in size of the terminal electrodes on the left side and the right side of the upper surface of the chip. Thus, by modification of the size of the terminal electrodes on the upper surface of the chip, the direction in which the wound coil is pulled out can be adjusted. Therefore, it is not necessary to provide a forming step or steps for a directional marker to eliminate the number of steps of production. In this case, there is no problem of property deficiency by the reasons set forth above.
Further, in another (a fifth) embodiment of the invention, the coil is positioned close to the upper surface of the chip (i.e., closer to the upper surface than the lower surface) so that a predetermined distance is obtained between the coil and the terminal electrode on the lower surface of the chip.
As explained above, although a stray capacitance between the coil and the terminal electrodes on the upper surface of the chip is reduced, a stray capacitance relative to the lower surface of the chip is maintained. This is due to the fact that the extended portion of the terminal electrodes on the lower surface of the chip could not be formed as small as desired in order to provide a desired bonding strength at the time of mounting or packaging. Thus, in the fifth embodiment of this invention shown in FIG. 7, the coil is formed at the position adjacent to, or closer to, the upper surface of the chip where the terminal electrodes are small so that there is less influence of a stray capacitance, and the distance relative to the lower surface of the chip is increased. By this structure (structure of FIG. 7), reduction of the stray capacitance is achieved with a large size of the terminal electrodes having a suitable bonding strength being maintained.
In a sixth embodiment of the invention, the coil is formed in an expanded posture toward the sides of the chip where no terminal electrode is formed. If the coil is exposed from the side surface of the chip, the exposed portion of the coil is subject to an insulating treatment.
As shown in FIGS. 8, 9(a), 9(b) and 10, the coil extends toward the side surfaces of the chip where no terminal electrode is formed and less stray capacitance is generated so that a coil area is expanded. This structure permits an increase in the inductance value (L-value) with the resonance frequency being maintained at a high level. Further, since the same high level of L-value can be achieved by a relatively small number of windings, the number of the steps for a coil manufacturing process can be reduced.
Further, if the coil is largely extended so that its side portion is exposed on the side of the chip, it is desired that the exposed portion be insulated by resins or the like for the purpose of obtaining reliability.
In a seventh aspect of the present invention, there is provided a method of forming a laminated inductor, comprising laminating a plurality of conductive patterns with an electrically insulating layer (1) being superposed between the conductive patterns to form a plurality of coils (3) at one time to thereby provide a laminated block (21). The laminated block (21) is cut in the direction of exposure of a pulled-out pattern of the coil (3) to thereby form a plurality of block chips (22) having cut surfaces (22a, 22b). Conductive layers (24, 25) are formed on the side of both of the cut surfaces, and the block chip (22) is cut into chip units.
In the forming method of the invention described above, the electrodes are formed on the longitudinal structure of the block chips and in the process of production of the electrodes, a chip holding portion can be obtained for supporting the chips. Therefore, the method is effective for, ind has advantages in, production of the electrode of micro-miniaturized chips.
In an eighth aspect of the invention, there is provided a new laminated inductor comprising a laminated structure of a plurality of electrically insulating layers (2) and a plurality of conductive patterns. The conductive patterns are connected with each other at the ends thereof to form a coil (3) in an electrically insulating layer body, the coil being superimposed in a laminating direction. The terminal electrodes (4, 5) are formed on chip end surfaces and a chip lower surface for connecting therewith the coil, and an extended conductive layer is formed around an end surface of the chip for forming thereon the terminal electrode.
By forming the extended or overlapping conductive layer, a reliable coupling is made between the electrode on the end of the chip and the electrode of the lower surface of the chip. The overlapping layer is preferably made as small as possible and practically 50-100 xcexcm is preferred.
In a ninth embodiment of the invention, the terminal electrodes on the lower surface of the chip are formed during the process of the lamination, and the terminal electrodes on the end surface of the chip are formed after chamfering of each chip after sintering.
By the chamfering, entangling of the chips can be prevented at the time of treatment or handling of the chips. After chamfering, provision of the extended or overlapping layer portion ensures a reliable connection between the electrodes of the chip end surface and the electrodes of the upper and lower surfaces of the chips.